Modification and electrical characterization of self-assembled monolayer/silicon samples with and without an interfacial oxide layer by the use of scanning probe microscopes
Han, Jiwon; Sano, Hikaru; Ichii, Takashi; Murase, Kuniaki; Sugimura, Hiroyuki
Japan

Scanning probe microscopy (SPM) is powerful for nanopatterning and characterization of material surfaces including self-assembled monolayer (SAM)/Si samples [1]. In particular, both scanning capacitance microscopy (SCM) and Kelvin-probe force microscopy (KFM) are promising in order to characterize electrical properties of semiconductor surface and interfaces. We have conducted patterning SAM/Si samples by locally injecting current from a conductive AFM probe. In this presentation, we report on electrical characterization of patterned features on the samples by the use of SCM and KFM.
Two types of SAM/Si samples with and without an interfacial oxide layer between SAM and Si were used in this research. The first was an octadecylsilyl (ODS) SAM, prepared by a vapor phase method, on Si (n-type resistivity of 4 - 6 Ω cm) covered with a 2-nm thick oxide. The second was a hexadecyl (HD) SAM formed through a thermal reaction of 1-hexadecene with a hydrogen-terminated Si substrate (n-type resistivity of 1 - 10 Ω cm). The SAM/Si samples were modified by applying a sample bias in the range of 1 - 9 V using a Pt-Ir coated AFM Si probe. In the case of the ODS-SAM/Si which had the interfacial oxide layer, distinct SCM and KFM contrasts have been observed at all the regions where were current-injected with applying the sample bias of 1 - 9 V. On the contrary, in the case of the HD-SAM/Si which had no oxide layer, regions fabricated with the sample bias of 6 - 9 V were detectable by SCM and KFM. The origin of the SCM and KFM contrasts of the regions modified at this high voltage range is most likely anodic degradation of the SAMs and oxidation of the Si substrates, while the contrasts appeared only on the ODS-SAM/Si sample with the surface modification at the low bias range of 1 - 5 V is considered probably due to charge trapping in the oxide layer and/or at the SAM/oxide interface.
[1] H. Sugimura, Int. J. Nanotechnology, 2 (2005) 314.
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